1. Field of the Invention
The present invention relates to the field of watermarking electronic circuits and, in particular, to the watermarking of integrated circuits, like FPGA (field programmable gate arrays) or ASIC (application specific integrated circuits) designed based on IP cores (Intellectual Property cores).
2. Description of Related Art
In the 1970s, only basic functions like discrete logical gates were implemented on integrated circuits. With improvements in the chip manufacturing, the size of the transistors was drastically reduced and the maximum size of a die was increased as well. Now it is possible to integrate one billion transistors on one chip, as described bys Xilinx, Inc., “Next-Generation Virtex Family From Xilinx to top one Billion Transistor Mar”, 03131_nextgen.htm, available at: www.xilinx.com/prs_rls/silicon_vir/, in the following referred to as [1]. On the other hand, the market requires shorter product cycles. The only solution is to reuse cores, which have been written for other projects or were purchased from other companies. The number of companies that produce just cores constantly increases. The advantages of reuse of IP cores are enormous. E.g., they offer a modular concept and fast development-cycles.
IP cores are licensed and distributed like software. One problem of the distribution of IP cores is the lack of protection against unlicensed usage. As the cores are provided, e.g., as netlist data, they can be easily copied like software. So there is only a small effort to get the illegal core to function.
To protect their IP cores, some core suppliers encrypt their cores and deliver special development tools, which can handle encrypted cores. The disadvantage is that common tools cannot handle encrypted cores and that the shipped tools can be modified.
Another approach for protection is to hide a signature into the core, a so-called watermark, which can be used as a proof of the original ownership. There exist many concepts and approaches on the issue of implementing a watermark into a core. But most of these concepts are not applicable due to the lack of verification capabilities. A good verification strategy is that the signature (watermark) can be read out only using the bought product. So no extra files or information must be obtained from the accused company.
Hiding a unique signature into user data, such as pictures, video, audio, text, program code, or IP cores is called watermarking. Embedding a watermark into multimedia data is achieved by altering the data slightly at points, where human sense organs have lower perceptions sensitivity. For example, one can remove frequencies, which cannot be perceived by the human ear by coding an audio sequence into an MP3 file. Now, it is possible to hide a signature into these frequencies, without decreasing quality of the coded audio sequence, as described by L. Boney, A. H. Tewfik, and K. N. Hamdy, “Digital watermarks for audio signals,” in International Conference on Multimedia Computing and Systems, 1996, pp. 473-480, available at: citeseer.ist.psu.edu/boney96digital.html, in the following referred to as [2].
The watermarking of IP cores is different from multimedia watermarking, because the user data, which represents the circuit, must not be altered, since functional correctness must be preserved. Watermarking procedures can be categorized into two groups of methods: additive methods and constraint-based methods.
Additive methods have in common that the signature is added to the functional core, for example, by using unused lookup tables in a FPGA, as described by J. Lach, W. H. Mangione-Smith, and M. Potkonjak, “Signature hiding techniques for FPGA intellectual property protection,” in proceedings of ICCAS, 1998, pp. 186-189, available at: citeseer.ist.psu.edu/lach98signature.html, in the following referred to as [3]. In other words, additive methods add additional logic or elements to those elements, which are required for those operations the integrated circuit of IP core is designed for.
The constraint-based methods were originally introduced by Kahng, Lach, Mangione-Smith, Mantik, Markov, Potkonjak, Tucker, Wang, and Wolfe, “Constraining-based watermarking technique for design IP protection,” IBEETCAD: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, 2001, available at: citeseer.ist.psu.edu/kahng01constraintbased.html, in the following referred to as [4], and restrict the solution space of an optimization algorithm by setting additional constraints, which are used to encode the signature.
Some method for constraint-based watermarking in FPGAs include exploiting the wire wrap of a scan-chain [5], preserving nets during logic synthesis [6], placing constraints for CLBs (Configurable Logic Blocks) in odd/even rows [7], or routing constraints with unusual routing resources [7].
A method exploiting the wire wrap of a scan-chain is described by D. Kirovski and M. Potkonjak, “Intellectual property protection using watermarking partial scan chains for sequential logic test generation,” in ICCAS, 1998, available at: citeseer.ist.psu.edu/218548.html, in the following referred to as [5]. An example preserving nets during logic synthesis is explained by D. Kirovski, Y.-Y. Hwang, M. Potkonjak, and J. Cong. “Intellectual property protection by watermarking combinational logic synthesis solutions,” in proceedings of ICCAS, 1998, pp. 194-198, available at: citeseer.ist.psu.edu/article/kirovski98intellectual.html, in the following referred to as [6]. An example placing constraints for CLB (configurable logic blocks) is explained by A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, “Robust IP watermarking methodologies for physical design,” in Design Automation Conference, 1998, pp. 782-787, available at: citeseer.ist.psu.edu/kahng98robust.html, in the following referred to as [7]. An example based on routing constraints with unusual routing resources can also be found in [7].
The major drawback of these approaches are the limitations of the verification possibilities of the watermarked core. With a good watermarking strategy, the verification can be done only with the given product without additional information from the producer. The bit file of an FPGA can be extracted by wire tamping the communication between the PROM (programmable read-only memory) and the FPGA, for example, when a SRAM (static random access memory) FPGA loads the bit file from the PROM. But only the approach presented in [3] has the possibility to detect the watermark from these bitfiles.
Some FPGA suppliers provide an option to encrypt the bitstream. The bitfile is stored in the PROM in encrypted form and will be decrypted inside the FPGA. Monitoring the communication between PROM and FPGA in this case is useless, because only the encrypted file will be transmitted. In this case, only the verification over a scan chain is possible [5].
Also the introduced approaches at the HDL (Hardware Description Language) and netlist-levels turn out not to be applicable due to the lack of verification possibilities. The only exception is the scan chain approach, but a scan chain is very unusual in FPGA designs. However, many cores are delivered in HDL or at the netlist level, so a watermarking strategy for these cores would be very useful.
Thus, it can be summarized that the aforementioned approaches for inserting watermarks to FPGAs add overhead, e.g. additional elements not used for the normal operation of the integrated circuit, or limit the optimization of the integrated circuits due to constraints used for watermarking or identification of these integrated circuits. The major disadvantage of the aforementioned approaches are the limited possibilities to detect whether the integrated circuit has a watermark and if the integrated circuit has a watermark, to identify which watermark this particular integrated circuit has. Within this document a watermark is also referred to as or signature or identifier. These approaches, for example, all lack the possibility to detect a watermark by only analyzing the specific integrated circuit, for example, a FPGA or an ASIC or a specific IP core on one of the aforementioned integrated circuits.